As I stated it’s MORE complex today, not less, as the downvoters of my posts seem to refuse to acknowledge.
The reason you’re getting downvoted is because you’re saying that “64-bit CPU” means something different than is universally acknowledged that it means. It means pointer width.
Yes, other numbers are important. Yes, other numbers can be listed in places. No, it’s not what people mean when they say “X-bit CPU”.
claiming that new CPU architectures haven’t increased in bit width for 30 years is simply naive and false, because they have in many more significant ways than the base instruction set.
RV128 exists. It refers to pointer width. Crays existed, by your account they were gazillion-bit machines because they had quite chunky vector lengths. Your Ryzen does not have a larger “databus” than a Cray1 which had 4096 bit (you read that right) vector registers. They were never called 4096 bit machines, they Cray1 has a 64-bit architecture because that’s the pointer width.
Yes, the terminology differs when it comes to 8 vs. 16-bit microcontrollers. But just because data bus is that important there (and 8-bit pointers don’t make any practical sense) doesn’t mean that anyone is calling a Cray a 4096 bit architecture. You might call them 4096 bit vector machines, and you’re free to call anything with AVX2 a 256-bit SIMD machine (though you might actually be looking at 2x 128-bit ALUs), but neither makes them 64-bit architectures. Why? Because language is meant for communication and you don’t get to have your own private definition of terms: Unless otherwise specified, the number stated is the number of bits in a pointer.
64-bit integers, memory addresses, or other data units[a] are those that are 64 bits wide. Also, 64-bit central processing units (CPU) and arithmetic logic units (ALU) are those that are based on processor registers, address buses, or data buses of that size.
It also states Address bus, but as I mentioned before, that doesn’t exist. So it boils down to instruction set as a whole requiring 64 bit processor registers and Databus.
Obviously 64 bits means registers are 64 bit, the addresses are therefore also 64 bit, otherwise it would require type casting every time you need to make calculations on them. But it’s the ability to handle 64 bit registers in general that counts, not the address registers. which is merely a byproduct.
You were arguing the definition of “X-bit CPU”. We’re not talking about “X-bit ALU”. It’s also not up to contention that “A 64-bit integer is 64 bit wide”. So, to the statement:
Also, 64-bit central processing units (CPU) and arithmetic logic units (ALU) are those that are based on processor registers, address buses, or data buses of that size.
This does not say which of “processor register, address buses, or data buses” applies to CPU and which to ALU.
Obviously 64 bits means registers are 64 bit, the addresses are therefore also 64 bit,
Having 64 bit registers doesn’t necessitate that you have 64 bit addresses. It’s common, incredibly common, for the integer registers to match the pointer width but there’s no hard requirement in theory or practice. It’s about as arbitrary a rule as “Instruction length must be wider than the register size”, so that immediate constants fit into the instruction stream, makes sense doesn’t it… and then along come RISC architectures and split load immediate instructions into two.
otherwise it would require type casting every time you need to make calculations on them
Where did you get that from? Because that’s false, please show me dokumentation for that.
64 bit always meant the ability to handle 64 bit wide instructions, and because the architecture is 64 bit, the pointers INTERNALLY are 64 bit, but effectively they are only for instance 40 bit when accessing data.
Your claim about pointer width simply doesn’t make any sense.
That the CPU should be called by a single aspect they can’t actually handle!!! That’s moronic.
The reason you’re getting downvoted is because you’re saying that “64-bit CPU” means something different than is universally acknowledged that it means. It means pointer width.
Yes, other numbers are important. Yes, other numbers can be listed in places. No, it’s not what people mean when they say “X-bit CPU”.
RV128 exists. It refers to pointer width. Crays existed, by your account they were gazillion-bit machines because they had quite chunky vector lengths. Your Ryzen does not have a larger “databus” than a Cray1 which had 4096 bit (you read that right) vector registers. They were never called 4096 bit machines, they Cray1 has a 64-bit architecture because that’s the pointer width.
Yes, the terminology differs when it comes to 8 vs. 16-bit microcontrollers. But just because data bus is that important there (and 8-bit pointers don’t make any practical sense) doesn’t mean that anyone is calling a Cray a 4096 bit architecture. You might call them 4096 bit vector machines, and you’re free to call anything with AVX2 a 256-bit SIMD machine (though you might actually be looking at 2x 128-bit ALUs), but neither makes them 64-bit architectures. Why? Because language is meant for communication and you don’t get to have your own private definition of terms: Unless otherwise specified, the number stated is the number of bits in a pointer.
https://en.wikipedia.org/wiki/64-bit_computing
It also states Address bus, but as I mentioned before, that doesn’t exist. So it boils down to instruction set as a whole requiring 64 bit processor registers and Databus.
Obviously 64 bits means registers are 64 bit, the addresses are therefore also 64 bit, otherwise it would require type casting every time you need to make calculations on them. But it’s the ability to handle 64 bit registers in general that counts, not the address registers. which is merely a byproduct.
You were arguing the definition of “X-bit CPU”. We’re not talking about “X-bit ALU”. It’s also not up to contention that “A 64-bit integer is 64 bit wide”. So, to the statement:
This does not say which of “processor register, address buses, or data buses” applies to CPU and which to ALU.
Having 64 bit registers doesn’t necessitate that you have 64 bit addresses. It’s common, incredibly common, for the integer registers to match the pointer width but there’s no hard requirement in theory or practice. It’s about as arbitrary a rule as “Instruction length must be wider than the register size”, so that immediate constants fit into the instruction stream, makes sense doesn’t it… and then along come RISC architectures and split load immediate instructions into two.
Processors don’t typecast. Please stop talking.
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Where did you get that from? Because that’s false, please show me dokumentation for that.
64 bit always meant the ability to handle 64 bit wide instructions, and because the architecture is 64 bit, the pointers INTERNALLY are 64 bit, but effectively they are only for instance 40 bit when accessing data.
Your claim about pointer width simply doesn’t make any sense.
That the CPU should be called by a single aspect they can’t actually handle!!! That’s moronic.
People literally use the word “literally” to mean figuratively. It doesn’t make any sense. One might even call it moronic.
But it’s the way it’s done. Deal with it.